ESD protection has been a main concern in the reliability of integrated circuit (IC) products in submicron complimentary metal-oxide-silicon (CMOS) technologies. For example, N-type metal metal-oxide-silicon (NMOS) and P-type metal-oxide-silicon (PMOS) transistors in input/output (I/O) buffers of a CMOS IC are often directly connected to input pads of the IC, causing the CMOS input buffers to be vulnerable to ESD damage.
A conventional MOS input/output (I/O) buffer transistor 110 and I/O pad 180 are shown in FIG. 1. Transistor 110 comprises a source 112, a drain 114 and a gate 116. The source and drain are regions of N-type conductivity formed in a substrate or well of P-type conductivity. The substrate or well, which is sometimes referred to as the body, is represented schematically in FIG. 1 by element 118. As shown in FIG. 1, source 112 and body 118 are connected to ground and drain 114 is connected to I/O pad 180. As will be appreciated by those skilled in the art, a typical integrated circuit has numerous such I/O pads and I/O buffers.
The circuit of FIG. 1 provides ESD protection by triggering a parasitic lateral bipolar transistor inherent in the MOS structure where the source and drain regions of the MOS transistor constitute the emitter and collector of the lateral bipolar transistor and the substrate constitutes the base. See, for example, A. Amerasekera and C. Durvery, ESD in Silicon Integrated Circuits, pp. 81-95, 137-148 (2d Ed., Wiley, 2002), which is incorporated herein by reference.
In the circuit of FIG. 1, P-type body 118 and N-type source region 112 form a first P-N junction and P-type body 118 and N-type drain region 114 form a second P-N junction. As a result, a parasitic lateral bipolar transistor is present in transistor 110 having a base-emitter junction that is the first P-N junction and a base-collector junction that is the second P-N junction. In the event of a positive voltage ESD event on the input pad, the second P-N junction is driven into breakdown and avalanche and the parasitic transistor is triggered into conduction to discharge the ESD pulse.
Unfortunately, the width of the parasitic bipolar transistor in some I/O buffers is too small to provide effective ESD protection. In addition, if an I/O buffer is used alone, it typically requires a salicide block mask or some kind of ballasting technique such as a back-end ballast (BEB). Such techniques also increase the size of the I/O buffer. To avoid the use of such techniques, it has been proposed to use a silicon controlled rectifier (SCR) in parallel with the I/O buffer. FIG. 2 illustrates such a circuit comprising an MOS I/O buffer transistor 110, an SCR 130, a resistor 160 and an I/O pad 180. Transistor 110 and I/O pad 180 are the same elements as in FIG. 1 and have been numbered the same. SCR 130 is connected between I/O pad 180 and ground. It comprises an NPN transistor 131 and a PNP transistor 141 each having an emitter 133, 143, a base 134, 144 and a collector 135, 145, respectively, connected so that the base of the NPN transistor is connected to the collector of the PNP transistor and the base of the PNP transistor is connected to the collector of the NPN transistor. Resistor 160 isolates SCR 130 from I/O buffer transistor 110. Unfortunately, for resistor 160 to be effective in isolating SCR 130 from I/O buffer 110, its resistance value must be 20 ohms or more. A resistance value this high significantly limits the speed of signals on the I/O pad.